Abstract
The rapid and aggressive development of modern nano/microelectronics relies on the introduction of novel device architectures and channel materials. Unlike the more tangible product parameters, such as performance or power consumption, reliability specifications are often neither disclosed nor considered by the typical end-user. In reality, however, reliability is the essential metric required for the introduction of each new VLSI node. Therefore, predictive reliability models, which can thoroughly address degradation behavior of future (potentially not yet existing) transistors, are of extreme importance. To ensure predictive capabilities, such models should rely on a very thorough description of the physical picture behind degradation mechanisms. Quite unfortunately, this picture is very complex and includes such non-trivial sub-problems as modeling of defects and their activation/generation rates, carrier transport simulations (because carriers interact with defects and their precursors, thereby resulting in damage accumulated inside a device), and modeling of the characteristics of the damaged devices to quantify how degradation deteriorates the transistor performance. All these tasks are very complex and require extensive computational resources.
Luckily, over the last decade, machine learning (ML) has become a powerful platform for tackling numerically expensive problems at substantially reduced computational burden. To be more specific, a number of ML-focused activities have been driven at imec including (but not limited by): physics-informed (PI) ML for semiconductor manufacturing, ML-aided multiscale thermal simulation of integrated circuits, ML-assisted extraction of parameters of traps responsible for random telegraph noise (one of the important reliability issues), and ML-aided ab initio calculations of defect properties. Further progress in boosting computational efficiency and accuracy is to be achieved by employing physics-informed machine learning (PIML). This strategy is based on integration of physical and mathematical concepts – aimed at improving a learning algorithm and catalyzing its performance – in the ML framework.
The general goal of this PhD work is to develop a PI learning framework for predictive modeling of the most detrimental reliability phenomena plaguing modern transistors – hot-carrier degradation, bias temperature instability, and OFF-state stress. Dramatic reduction of computational time should be achieved by applying PIML to the carrier transport problem. The training phase will be carried out by employing an extensive set of simulation data (over a broad range of transistor architectures and bias conditions) obtained with our transport simulator ViennaSHE. Another opportunity for optimization is related to accelerated modeling of the degraded device which should enable large-scale simulations considering random distributions throughout a transistor of doping atoms and activated traps, as well as other sources of variability. Finally, employment of PIML is expected not only to drastically reduce computational time but also allow using predictive models for device reliability at the DTCO level, thereby making them attractive to device and circuit designers.
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